Sense amplifier with read circuit for compute-in-memory
US12322435B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2022 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Mar 25, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device including a memory array configured to store data, a sense amplifier circuit coupled to the memory array, and a read circuit coupled to the sense amplifier circuit, wherein the read circuit includes a first input that receives a read column select signal for activating the read circuit to read the data out of the memory array through the read circuit during a read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.