Fluid channel geometry optimizations to improve cooling efficiency
US12322677B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2024 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Jul 25, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/80896
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The cold plate has a perimeter sidewall, a top portion and pairs of opposing cavity sidewalls. The perimeter sidewall extends downwardly from the top portion to a backside of the semiconductor device to define a perimeter of the cold plate. Each pair of opposing cavity sidewalls extends downwardly from the top portion towards the backside of the semiconductor device to define a coolant chamber volume therebetween. A distance between each pair of opposing cavity sidewalls in a direction parallel with the backside of the semiconductor device defines a width of a corresponding coolant chamber volume and a spacing between adjacent coolant chamber volumes, wherein the ratio of width to spacing is about 1:1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.