Method of manufacturing electronic devices and corresponding electronic device
US12322684B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 26, 2022 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Aug 18, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/107
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A substrate includes electrically-conductive tracks. A semiconductor chip is arranged on the substrate and electrically coupled to selected ones of the electrically-conductive tracks. Containment structures are provided at selected locations on the electrically-conductive tracks, where the containment structures have respective perimeter walls defining respective cavities. Each cavity is configured to accommodate a base portion of a pin holder. These pin holders are soldered to the electrically-conductive tracks within the cavities defined by the containment structures. Each containment structure may be formed by a ring of resist material configured to receive solder and maintain the pin holders in a desired alignment position.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.