Diffusion-break region in stacked-FET integrated circuit device
US12324237B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2022 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Feb 14, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked field effect transistor (stacked-FET) device includes a first layer comprising at least one first layer transistor structure comprising a plurality of first layer terminals, a diffusion break dielectric fill region adjacent to one of the first layer terminals, a second layer overlying and adjacent to the first layer and comprising at least one second layer transistor structure comprising a plurality of second layer terminals, and a contact wiring between the first layer and the second layer passing through the diffusion break dielectric fill region of the first layer and connecting with one of the second layer terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.