Vertical memory devices and methods for operating the same
US12327592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2024 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | Apr 10, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for performing an erasing operation on a memory device is provided. The memory device includes a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar, and a bit line formed above the drain cap. A first positive voltage bias is applied to the bottom select gate. A second positive voltage bias is applied to the plate line. The first positive voltage bias to the bottom select gate is reduced. A negative voltage bias is applied to the source line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.