Memory devices having vertical transistors and methods for forming the same
US12328867B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2021 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | Sep 21, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1436
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In certain aspects, a memory device includes a vertical transistor, a storage unit, and a bit line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and in contact with a second terminal. The second terminal is another one of the source and the drain that is formed on all sides of a protrusion of the semiconductor body. The bit line is separated from the channel portion of the semiconductor body by the second terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.