Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures

US12328927B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Gilbert Dewey · Beaverton, US
• Nazila Haratipour · Hillsboro, US
• Siddharth Chouksey · Portland, US
• Arnab Sen Gupta · Beaverton, US
• Christopher J. Jezewski · Portland, US
• I-Cheng Tung · Hillsboro, US
• Matthew V. Metz · Portland, US
• Anand S. Murthy · Beaverton, US

Key dates

• Filing date: Sep 25, 2020
• Grant date: Jun 10, 2025
• Expiry date: Oct 9, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/013
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Low resistance and reduced reactivity approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is on the first or second semiconductor source or drain structure, the source or drain contact including an alloyed metal barrier layer and an inner conductive structure.