Buffer that supports burst transfers having parallel CRC and data transmissions
US12332739B2 · kind B2 · utility
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2References
18Claims
0Family size
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Key dates
| Filing date | May 21, 2021 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Aug 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3041
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is described. The method includes a buffer semiconductor chip receiving a plurality of data signals. The method includes the buffer chip calculating first CRC information from the plurality of data signals. The method includes the buffer chip transmitting the plurality of data signals in parallel with the first CRC information if a read burst transfer sequence is being performed, the buffer chip receiving second CRC information in parallel with the plurality of data signals and comparing the first CRC information with the second CRC information if a write burst transfer sequence is being performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.