Reducing bit error rate in memory devices
US12333154B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2023 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Jul 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device in a memory sub-system performs a first media scan operation with respect to a plurality of memory pages addressable by the ordinary wordline, wherein each page of the plurality of memory pages is contained by a respective management unit, and responsive to determining that a value of a data state metric of a memory page of the plurality of memory page addressable by the ordinary wordline satisfies a specified condition, performs a first media management operation with respect to a management unit containing the memory page. The processing device further performs a second media scan operation with respect to a plurality of memory pages addressable by the mandatory wordline, wherein each page of the plurality of memory pages is contained by the respective management unit, and responsive to determining that a value of the data state metric of a memory page of the plurality of memory page addressable by the mandatory wordline satisfies the specified condition, performs a second media management operation with respect to the management unit containing the memory page.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.