Memory bit cell for in-memory computation
US12333357B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | May 11, 2021 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Jan 24, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.