Inner spacer formation in multi-gate transistors
US12336252B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2022 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Jul 21, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02332
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor structure includes forming a fin on a semiconductor substrate. The fin includes channel layers and sacrificial layers stacked one on top of the other in an alternating fashion. The method also includes removing a portion of the fin to form a first opening and expose vertical sidewalls of the channel layers and the sacrificial layers, epitaxially growing a source/drain feature in the first opening from the exposed vertical sidewalls of the channel layers and the sacrificial layers, removing another portion of the fin to form a second opening to expose a vertical sidewall of the source/drain feature, depositing a dielectric layer in the second opening to cover the exposed vertical sidewall of the source/drain feature, and replacing the sacrificial layers with a metal gate structure in the second opening. The dielectric layer separates the source/drain feature from contacting the metal gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.