Low stress films for advanced semiconductor applications
US12341002B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2020 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | Feb 5, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Films that can be useful in large area gap fill applications, such as in the formation of advanced 3D NAND devices, involve processing a semiconductor substrate by depositing on a patterned semiconductor substrate a doped silicon oxide film, the film having a thickness of at least 5 μm, and annealing the doped silicon oxide film to a temperature above the film glass transition temperature. In some embodiments, reflow of the film may occur. The composition and processing conditions of the doped silicon oxide film may be tailored so that the film exhibits substantially zero as-deposited stress, substantially zero stress shift post-anneal, and substantially zero shrinkage post-anneal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.