Method for manufacturing through vias using amorphization to adjust etching rate
US12341060B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Apr 19, 2022 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | May 29, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor structure is provided. The method may include several operations. A first layer is formed over a first region and a second region of a substrate. A first etching is performed on the first layer, thereby forming a first trench in the first region and a second trench in the second region. A first amorphization is performed on the first layer in the second region. A second etching is performed on the first layer, wherein an etching rate of the second etching in the second region is greater than an etching rate of the second etching in the first region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.