Contact resistance reduction in transistor devices with metallization on both sides

US12342574B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Koustav Ganguly · Beaverton, US
• Ryan Keech · Portland, US
• Subrina RAFIQUE · Hillsboro, US
• Glenn A. Glass · Portland, US
• Anand S. Murthy · Beaverton, US
• Ehren Mannebach · Beaverton, US
• Mauro J. Kobrinsky · Portland, US
• Gilbert Dewey · Beaverton, US

Key dates

• Filing date: Jun 25, 2020
• Grant date: Jun 24, 2025
• Expiry date: Jan 31, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0151
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.