Test pattern generation using multiple scan enables

US12345764B2 · kind B2 · utility

Assignee

• STMicroelectronics International N.V. · NL

Inventors

• Shiv Kumar Vats · Greater Noida, IN
• Umesh Chandra Srivastava · Greater Noida, IN
• Venkata Narayanan Srinivasan · Greater Noida, IN

Key dates

• Filing date: Jun 20, 2023
• Grant date: Jul 1, 2025
• Expiry date: Aug 10, 2043

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318555
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An integrated circuit includes a first set and a second set of scan flip flops, a circuit under test, and a controller. Each scan flip flop of the first set includes a scan enable input coupled to a first scan enable signal. The circuit under test includes logic elements downstream of the first set. The second set includes at least one scan flip flop downstream of the logic elements. Each scan flip flop of the second set includes a scan enable input coupled to a second scan enable signal. The controller is configured to test the logic elements by shifting test patterns into the first set while asserting both the first and second scan enable signal, launching the test patterns, and capturing results from the second set while continuing to assert the first scan enable signal and deasserting the second scan enable signal.