Shiv Kumar Vats
6Patents
2h-index
5Co-inventors
36Inventor score
Filing activity: Apr 18, 2019 → Aug 11, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10802077B1 | Test circuit for dynamic checking for faults on functional and BIST clock paths to memory in both ATPG and LBIST modes | Physics | 6 | Active |
| US11714131B1 | Circuit and method for scan testing | Physics | 2 | Active |
| US11726140B2 | Scan circuit and method | Physics | 1 | Active |
| US12345764B2 | Test pattern generation using multiple scan enables | Physics | 0 | Active |
| US12366605B2 | Area, cost, and time-effective scan coverage improvement | Physics | 0 | Active |
| US12360161B2 | Scan circuit and method | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.