Interconnect fabric link width reduction to reduce instantaneous power consumption
US12346189B2 · kind B2 · utility
0Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 2024 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | May 7, 2044 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.