Method and apparatus for memory chip row hammer threat backpressure signal and host side response
US12347507B2 · kind B2 · utility
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3References
21Claims
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Key dates
| Filing date | May 8, 2021 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Sep 24, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory chip includes row hammer threat detection circuitry. The memory chip includes an output. The memory chip includes backpressure signal generation circuitry coupled between the row hammer detection circuitry and the output. The backpressure signal generation circuitry is to generate a backpressure signal to be sent from the output in response to detection by the row hammer threat detection circuitry of a row hammer threat.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.