Etch rate modulation of FinFET through high-temperature ion implantation
US12347687B2 · kind B2 · utility
0Cited by
3References
19Claims
0Family size
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Key dates
| Filing date | Aug 21, 2020 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Jul 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device may include forming a plurality of fins extending from a buried oxide layer, wherein a masking layer is disposed atop each of the plurality of fins, and performing a high-temperature ion implant to the semiconductor device. The method may further include performing an etch process to remove the masking layer from atop each of the plurality of fins, wherein the etch process does not remove the buried oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.