Host verification for a memory device
US12353755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2024 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | May 9, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0688
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for host verification for a memory device are described. A memory device may receive a first value from a host device that is associated with an identification of the host device after an event. The memory device may transmit a second value to the host device that is based on the first value and comprises a random set of bits. The memory device may receive from the host device data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device. The memory device may also enable a functionality of the memory device based on the encrypted third value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.