Nonvolatile memory device including power gating circuit and input/output circuit of a nonvolatile memory device
US12354675B2 · kind B2 · utility
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12References
20Claims
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Key dates
| Filing date | Jan 23, 2023 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Sep 22, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An input/output circuit of a nonvolatile memory device and a nonvolatile memory device. The input/output circuit of a nonvolatile memory device includes a driver, which is configured to output data from the nonvolatile memory device to a data line, and a power gating circuit, which is connected between the driver and a power terminal or between the driver and a ground terminal and configured to block a leakage current of the driver. The power gating circuit includes a plurality of transistors electrically connected in parallel and having threshold voltages of different magnitudes, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.