Chip package structure and storage system
US12354941B2 · kind B2 · utility
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3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2022 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Sep 26, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1437
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package structure and a storage system are provided. The chip package structure includes a chipset, a first Re-Distribution Layer (RDL), and a bonding pad region. The chipset includes a plurality of chips distributed horizontally. The first RDL is disposed on a first surface of the chipset. The bonding pad region includes a plurality of bonding pads, the plurality of bonding pads are located on a side surface of the first RDL away from the chipset, and the plurality of bonding pads are connected to the plurality of chips through the first RDL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.