Staggered read recovery for improved read window budget in a three dimensional (3D) NAND memory array
US12362002B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2021 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Aug 16, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
At the end of or after a reading operation in a 3D (three dimensional) NAND array, the wordlines of the 3D NAND array can be transitioned to ground in a staggered manner. The 3D NAND array includes a 3D stack with multiple wordlines vertically stacked, including a bottom-most wordline, a top-most wordline, and middle wordlines between the bottom-most wordline and the top-most wordline. A controller that controls the reading can set the multiple wordlines to a high voltage at the end or after the reading operation and then transition a selected wordline of the multiple wordlines from the high voltage to ground prior to transitioning the other wordlines to ground. Thus, the controller will transition the other wordlines from the high voltage to ground after a delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.