Semiconductor structure, fabrication method and three-dimensional memory
US12362223B2 · kind B2 · utility
0Cited by
2References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 5, 2022 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Aug 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure, fabrication method and three-dimensional memory are disclosed. A method of fabricating a semiconductor structure includes providing a substrate including a first device region and a second device region; forming a plurality of first recesses in the first device region and a second recess in the second device region, the first recesses and the second recess being formed simultaneously; forming a first isolation trench in the first device region; and forming a second isolation trench in the second device region at a position of the second recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.