Memory device including circuitry under bond pads
US12362244B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2022 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Sep 22, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/85447
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments include apparatuses and methods of fabricating the apparatuses. One of the apparatuses includes a substrate of a semiconductor die; a memory cell portion located over a first portion of the substrate; a conductive pad portion located over a second portion of the substrate and outside the memory cell portion; and a sensor circuit including a portion located over the second portion of the substrate and under the conductive pad portion. The conductive pad portion includes conductive pads. Each of the conductive pads is part of a respective electrical path coupled to a conductive contact of a base outside the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.