Patent · US Active

Clock-gating in die-to-die (D2D) interconnects

US12362306B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Narasimha Lanka · Dublin, US
Debendra Das Sharma · Saratoga, US
Lakshmipriya Seshan · Sunnyvale, US
Gerald Pasdast · San Jose, US
Zuoguo Wu · San Jose, US
Swadesh Choudhary · Mountain View, US

Key dates

Filing date	Apr 29, 2022
Grant date	Jul 15, 2025
Priority date	—
Expiry date	Jul 18, 2043

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/15313
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Embodiments herein relate to action that are to be taken on various lanes of a die-to-die (D2D) interconnect in the event of clock-gating. Specifically, based on identification that a clock-gating event is to occur, physical layer (PHY) logic may direct PHY electrical circuitry to set the state of various of the lanes. In some embodiments, different actions may be taken based on whether the D2D interconnect is terminated or unterminated. Other embodiments may be described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.