Monolithic chip stacking using a die with double-sided interconnect layers
US12362325B2 · kind B2 · utility
0Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2023 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Sep 24, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided which comprises: a first die having a first surface and a second surface, the first die comprising: a first layer formed on the first surface of the first die, and a second layer formed on the second surface of the first die; a second die coupled to the first layer; and a plurality of structures to couple the apparatus to an external component, wherein the plurality of structures is coupled to the second layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.