Phase interpolator (PI) with clamping circuit to limit operation to range having optimal integral non-linearity and related methods
US12362902B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2023 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Nov 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00052
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-interpolator (PI) circuit generates an interpolated clock to capture data in a capture circuit at a target phase in a phase range between two reference clocks based on an interpolation code within a range of interpolation codes is described. A clamping circuit coupled to the PI circuit provides an interpolation code within a reduced range, where the integral non-linearity (INL) of the interpolated clocks is below a threshold, such that data capture based on the interpolated clock has a lower bit error rate (BER). As a result, the interpolated clock is generated within a reduced phase range corresponding to the reduced range of interpolation codes. When a target phase for an interpolated clock is outside the reduced phase range, the clamping circuit may adjust the target phase clock relative to a reference clock to adjust the target phase to be within the reduced phase range for improved BER.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.