Layout techniques and optimization for power transistors
US12363983B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2024 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Feb 20, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/471
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An example field effect transistor includes a substrate, a first source metal over the substrate, a second source metal over the substrate, and a drain metal positioned between the first source metal and the second source metal over a channel of the field effect transistor. The drain metal includes a drain metal body having a notched region between the first source metal and the second source metal over the channel, and the notched region defines a first projecting portion and a second projecting portion of the drain metal body. In one aspect, the first projecting portion and the second projecting portion are positioned on respective sides of the notched region. The notched region is a triangular-shaped notched region in one example.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.