Multi-threaded barrel processor using shared weight registers in a common weights register file
US12367043B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2019 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | May 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor comprising a barrel-threaded execution unit for executing concurrent threads, and one or more register files comprising a respective set of context registers for each concurrent thread. One of the one or more register files further comprises a set of shared weights registers common to some or all of the concurrent threads. The types of instructions defined in the instruction set of the processor include an arithmetic instruction having operands specifying a source and a destination from amongst a respective set of arithmetic registers of the thread in which the arithmetic instruction is executed. The execution unit is configured so as, in response to the opcode of the arithmetic instruction, to perform an operation comprising multiplying an input from the source by at least one of the weights from at least one of the shared weights registers, and to place a result in the destination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.