Technology to measure latency in hardware with fine-grained transactional filtration
US12367063B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2021 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Nov 22, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems and apparatuses may provide for technology that includes configuration registers to maintain state information, a filter coupled to the configuration registers, the filter to extract transactions of interest from a plurality of incoming transactions based on the state information, wherein the transactions of interest are extracted on a transaction-by-transaction basis, a first hardware path coupled to the filter, the first hardware path to generate a count of the transactions of interest on a cycle-by-cycle basis, a second hardware path coupled to the filter, the second hardware path to measure a total latency of the transactions of interest on the cycle-by-cycle basis, and an output interface coupled to the first hardware path and the second hardware path, the output interface to determine an average latency of the transactions of interest based on the count of the transactions of interest and the total latency of the transactions of interest.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.