Simultaneous lower tail verify with upper tail verify
US12367940B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2023 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Sep 29, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3486
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technology is disclosed herein for simultaneous lower tail program verify with upper tail verify. The memory system may apply a reference voltage to a word line following applying a program voltage to the word line. The memory system senses the first set of memory cells targeted for a first data state and the second set of memory cells targeted for a second data state. The memory system determines whether memory cells in the first set have a Vt greater than a maximum target Vt for the first data state based on the sensing of the first set of memory cells. The memory system also determines whether memory cells in the second set have a Vt less than a minimum target Vt for the second data state based on the sensing of the second set of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.