Diffusion barrier layer for conductive via to decrease contact resistance
US12368103B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jun 28, 2023 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Jun 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments relate to a semiconductor structure including a dielectric layer over a substrate. A conductive body is disposed within the dielectric layer. The conductive body has a bottom surface continuously extending between opposing sidewalls. A first liner layer is disposed between the conductive body and the dielectric layer. The first liner layer extends along the opposing sidewalls of the conductive body. The first liner layer is laterally offset from a central region of the bottom surface of the conductive body by a non-zero distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.