Electronic package and manufacturing method thereof
US12368116B2 · kind B2 · utility
0Cited by
0References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2022 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Jan 12, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73204
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package is provided, in which an electronic element that is electrically connected to a plurality of conductive vias and a functional part that has a hollow area are disposed on a photonic die that has the plurality of conductive vias and at least one external connection portion, where a cladding layer covers the electronic element and the functional part, such that the external connection portion is exposed from the hollow area and the cladding layer for an optical fiber to insert into the hollow area and connect to the external connection portion, so as to achieve the purpose of optoelectronic integration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.