Semiconductor device and method
US12368120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2023 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Dec 1, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16225
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.