Semiconductor structure, fabrication method and three-dimensional memory
US12376307B2 · kind B2 · utility
0Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2022 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Oct 24, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
Abstract
The present disclosure provides a semiconductor device. The semiconductor device includes a transistor in active area. The active area is in a substrate and comprises a recess, a surface of the recess having an offset from a surface of the substrate. The transistor comprises a gate electrode, the gate electrode comprising a first portion in the recess and a second portion outside the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.