Gate resistance improvement and method thereof
US12376326B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2023 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Jul 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.