Time-to-digital converters (TDC) employing a single-stage delay pair and noise shaping for wide input range and reduced quantization noise in a phase-locked loop (PLL)
US12379695B2 · kind B2 · utility
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21Claims
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Key dates
| Filing date | Apr 28, 2023 |
| Grant date | Aug 5, 2025 |
| Priority date | — |
| Expiry date | Nov 15, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/085
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Time-to-digital converters (TDC) employing a single-stage delay pair for a wide input range and reduced quantization noise in a phase-locked loop (PLL) and related fabrication methods are disclosed. Aspects disclosed in the detailed description include a single-stage Vernier time-to-digital converter (TDC) which mitigates the device mismatch impact and therefore avoids possible spurious tones in a fractional-N PLL application. Combined with a delta-sigma noise shaping stage and a ring-oscillator based coarse TDC, the invention achieves a good trade-off between resolution, detection range and PLL locking speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.