Semiconductor package, method of bonding workpieces and method of manufacturing semiconductor package
US12381191B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jan 12, 2024 |
| Grant date | Aug 5, 2025 |
| Priority date | — |
| Expiry date | Feb 2, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/1082
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first alignment pattern having a plurality of first scale patterns arranged in a first direction. The second semiconductor device is mounted over the first semiconductor device and includes a second alignment pattern having a plurality of second scale patterns arranged in a second direction parallel to the first direction, and a scale pitch of the first scale patterns is different from a scale pitch of the second scale patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.