Transistor arrangement with a lateral superjunction transistor device

US12382678B2 · kind B2 · utility

Assignee

• Infineon Technologies Dresden GmbH & Co. KG · DE

Inventors

• Rolf Weis · Dresden, DE
• Franz Hirler · Isen, DE
• Katarzyna Kowalik-Seidl · Munich, DE
• Marco Mueller · Villach, AT
• Anthony Sanders · Weißenfeld, DE

Key dates

• Filing date: May 17, 2022
• Grant date: Aug 5, 2025
• Expiry date: Aug 21, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/256

Abstract

A transistor arrangement is disclosed. The transistor arrangement includes a first transistor device and a second transistor device. The first transistor device and the second transistor device are connected in series and integrated in a common semiconductor body. The first transistor device is a lateral superjunction transistor device and is integrated in a first device region of the semiconductor body. The second transistor device is a lateral transistor device and is integrated in at least one second device region of the semiconductor body. The at least one second device region is spaced apart from the first device region.