Last level cache hierarchy in chiplet based processors
US12386750B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 29, 2023 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Dec 19, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/283
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An accelerated processor includes a processor core die including a plurality of compute units, the plurality of compute units including a first level (L1) cache. The accelerated processor also includes a plurality of memory cache dies coupled to the processor core die, the plurality of memory cache dies including a last level cache (LLC) such as a level 3 (L3) cache. The accelerated processor includes an LLC controller to issue a cache access request to the LLC and, based on a latency of the cache access request, direct the cache access request to a subset of the plurality of memory cache dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.