Enabling significant scaling of wordline switch with wordline dependent negative bitline voltage
US12387793B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2023 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Mar 8, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is provided and includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes a plurality of word line switch transistors that are electrically coupled with the plurality of word lines, where the plurality of word lines are grouped into a plurality of zones based on a size of a word line switch transistor associated with each word line of the plurality of word lines. The memory device also includes a bitline biasing circuit for providing a negative biasing voltage to a bitline corresponding to a memory cell of the selected word line during programming of the selected word line and the bitline biasing circuit is configured to set a magnitude of the negative biasing voltage based on which zone of the plurality of zones the selected word line is in.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.