Forming self-aligned vias and air-gaps in semiconductor fabrication
US12387983B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2022 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Jul 6, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/016
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.