Pitch translation architecture for semiconductor package including embedded interconnect bridge

US12388019B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Andrew Collins · Chandler, US
• Bharat P. Penmecha · Chandler, US
• Rajasekaran Swaminathan · Chandler, US
• Ram Viswanath · Phoenix, US

Key dates

• Filing date: Jun 21, 2024
• Grant date: Aug 12, 2025
• Expiry date: Jun 21, 2044

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/15313
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.