Patent · US Active

Three-dimensional memory devices and methods for forming the same

US12388036B2 · kind B2 · utility

0Cited by
7References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 21, 2021
Grant dateAug 12, 2025
Priority date
Expiry dateJul 18, 2043

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/14511
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. The first semiconductor structure or the second semiconductor structure further includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first peripheral circuit and the second peripheral circuit are stacked over one another.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.