Deterministic mixed latency cache
US12393518B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 29, 2021 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Sep 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and processing device for accessing data is provided. The processing device comprises a cache and a processor. The cache comprises a first data section having a first cache hit latency and a second data section having a second cache hit latency that is different from the first cache hit latency of the first data section. The processor is configured to request access to data in memory, the data corresponding to a memory address which includes an identifier that identifies the first data section of the cache. The processor is also configured to load the requested data, determined to be located in the first data section of the cache, according to the first cache hit latency of the first data section of the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.