DRAM computation circuit and method
US12394469B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2024 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Jun 14, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a boundary layer, a first circuit positioned on a first side of the boundary layer and including a DRAM array including a plurality of DRAM cells, a second circuit positioned on a second side of the boundary layer opposite the first side and including a computation circuit, the computation circuit including a sense amplifier circuit, and a plurality of bit lines coupled to the plurality of DRAM cells and the sense amplifier circuit. Each bit line of the plurality of bit lines includes a via structure positioned in the boundary layer and the plurality of DRAM cells of the first circuit positioned on the first side of the boundary layer is an entirety of the DRAM cells of the memory circuit coupled to the sense amplifier circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.