Memory cell and array structure of non-volatile memory and associated control method
US12400716B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2023 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Mar 18, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell is connected to a source line, a bit line, a word line, an assist gate line and an erase line. When a program action is performed, a weak programming procedure is first performed on the memory cell, and then a strong programming procedure is performed on the memory cell. When the weak programming procedure is performed, an on voltage is provided to the word line, a first program voltage is provided to the source line, a ground voltage is provided to the bit line, a first assist gate voltage is provided to the assist gate line, and a first erase line voltage is provided to the erase line. When the strong programming procedure is performed, a lower program voltage and a higher assist gate voltage are provided to the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.