Metal lines with low via-to-via spacing
US12400871B2 · kind B2 · utility
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10References
16Claims
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Key dates
| Filing date | Feb 20, 2020 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Jun 29, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is presented for employing double-patterning to reduce via-to-via spacing. The method includes forming a mandrel layer over a substrate, forming sacrificial hardmask layers over the mandrel layer defining a litho stack, creating a pattern in the litho stack, the pattern having a narrow section connecting two wider sections to define a substantially hour-glass shape, depositing a spacer assuming a shape of the pattern, and etching the litho stack to expose the mandrel layer and metal lines, wherein the metals lines define sharp distal ends reducing a distance between the metal lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.