Semiconductor device and method of manufacturing the same
US12400951B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 7, 2022 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Feb 11, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76844
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method of manufacturing a semiconductor device. The method includes: forming a first via and a second via on a semiconductor structure, wherein the semiconductor structure includes a first dielectric layer, a first barrier layer, a first metal, a second barrier layer, a second dielectric layer, a substrate, and a second metal; forming a third dielectric layer on the substrate and a bottom and the inner sidewalls of the first via and the second via; punching through the third dielectric layer on the bottom of the first via and the second via; forming a third barrier layer on the substrate and in the first via and the second via; removing oxides formed from the first metal and the second metal; forming a fourth barrier layer; and forming a conductive material in the first via and the second via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.